This invention relates to a solid-state image pickup apparatus in which static induction transistors (hereinafter referred to as SITs) which are capable of photoelectric conversion, amplification and switching are used.
To date, various types of solid-state image pickup apparatus, such as those using MOS transistors or those using charge coupled devices (CCDs) or BBDs been generally utilized. However, an apparatus using MOS transistors is disadvantageous in that its output signal level is very small and, hence, the signal-to-noise ratio thereof is small, and at the same time its photosensitivity is low. On the other hand, apparatuses using CCDs or BBDs display considerable losses of charge during the charge transfer operation and are difficult to produce.
To eliminate these defects, a type of solid-state image pickup apparatus such as that disclosed in Japanese Patent Publication No. 105672/1983 has been proposed, in which static induction transistors are used as picture elements.
The present inventors have proposed various solid-state image pickup apparatuses of improved types, based on the invention disclosed in the specification of the above publication. An example of one of them will be described below with reference to FIGS. 1A and 1B.
FIG. 1A shows the structure of one of picture elements of a solid-state image pickup apparatus constituted by SITs, and FIG. 1B shows the circuitry of this solid-state image pickup apparatus.
As shown in FIG. 1A, an n.sup.- epitaxial layer 2 which is to form a channel region is deposited on an n.sup.+ silicon substrate 1 which serves as the drain of an SIT. A shallow n.sup.+ source region is formed in the epitaxial layer 2, and this source region 3 is encircled by an p.sup.+ gate region within the epitaxial layer 2. A MOS capacitor 5 is formed on the gate region 4 in such a manner that a pulse can be supplied through this capacitor 5. This structure is also provided with a separation region 6 for separating picture elements from each other.
In the SIT which constitutes the picture element structured in this manner, when the gate region 4 is reversely biased, a depletion layer is formed outside the gate region 4. If light is introduced into this depletion layer to form hole-electron pairs, electrons are swept into the source region 3 and the drain region 1, and positive holes are accumulated in the gate region. The gate potential is thereby raised, and the current from the drain to the source is modulated by this change in this voltage, so that a signal which has been amplified in accordance with the intensity of the light is obtained.
SITs 10-11, 10-12, . . . 10-21, 10-22, . . . , . . . 10-44, which are disposed as illustrated in FIG. 1B, constitute picture elements which each have the structure shown in FIG. 1A. In this example, for convenience of description, the SITs are arranged in four rows horizontally and four columns vertically. Vertically-arranged sources of the SITs are connected in common to column lines 11-1, 11-2, . . . 11-4 which are connected to a video line 14 via transistors 13-1, 13-2, . . . 13-4 which constitute horizontal selection switches. The gates of the horizontal selection switches 13-1 to 13-4 are connected to a horizontal scanning circuit 15, and horizontal scanning pulses .PHI..sub.S1, .PHI..sub.S2, . . . .PHI..sub.S4 are applied to the gates.
On the other hand, horizontally-arranged gates of the SITs are respectively connected to row lines 12-1, 122, . . . 12-4 via capacitors. The row lines 12-1, 122, . . . 12-4 are connected to a vertical scanning circuit 16, and vertical scanning pulses .PHI..sub.G1, .PHI..sub.G2, . . . .PHI..sub.G4 are applied to the horizontally-arranged gates Of the SITs.
The other ends of the column lines 11-1, 11-2, . . . 11-4, whose one ends are connected to the horizontal selection transistors 13-1, 13-2, . . . 13-4, are respectively grounded via column line reset transistors 17-1, 17-2, . . . 17-4. Column line reset pulses .PHI..sub.R are applied in common to the gates of the column line reset transistors.
When a vertical scanning pulse is applied to the corresponding row line so as to select a row of picture elements, and when a column of picture elements is selected by a horizontal scanning pulse, an optical signal current at the picture element at the point of intersection of the selected row and column is read out. In this way, by outputting horizontal and vertical scanning pulses in succession, the picture elements are successively scanned to obtain signals corresponding to one frame.
FIG. 2 is a signal waveform chart showing the timing of pulses operating the above described solid-state image pickup apparatus, and FIG. 3 is a circuit diagram of components related to a SIT which constitutes one picture element in this apparatus.
Referring to FIG. 2, each of the vertical scanning pulses .PHI..sub.G ( .PHI..sub.G1, .PHI..sub.G2, .PHI..sub.G3) for selecting gates is a pulse having two different high levels, namely a read level V.sub.RD and a reset level V.sub.RS. The pulse is at the read level V.sub.RD during a horizontal scanning period ts for each row line, and at the reset level V.sub.RS during a horizontal blanking period t.sub.BL which follows the horizontal scanning period. Horizontal scanning pulses .PHI..sub.S (.PHI..sub.S1, .PHI..sub.S2, .PHI..sub.S3) for selecting sources go high level in each horizontal scanning period, thereby successively scanning the horizontally-arranged picture elements. The reset pulse .PHI..sub.R is at high level during each horizontal blanking period t.sub.BL to reset the picture elements which have been read out.
In the circuit diagram shown in FIG. 3, V.sub.G is the gate potential of a picture element SIT(T.sub.P); V.sub.S, the source potential; C.sub.GD, the parasitic capacitance between the gate and the drain; C.sub.GS, the parasitic capacitance between the gate and the source; C.sub.S, the stray capacitance of the source line; R.sub.ON, the on resistance of a horizontal selection MOS transistor T.sub.S ; and T.sub.R, a resetting MOS transistor.
FIG. 4 shows the changes with time in the gate potential V.sub.G and the source potential V.sub.G of a picture-element SIT when the horizontal scanning pulse .PHI..sub.S, the vertical scanning pule .PHI..sub.G and the reset pulse .PHI..sub.R are applied to the picture-element SIT in the solid-state image pickup apparatus. .PHI..sub.B represents the built-in voltage between the gate and the source, which will be described later.
The operation of the conventional apparatus at different points in time will be described below with reference to the accompanying drawings.
(1) At a time t.sub.1
.PHI..sub.R reaches high level when .PHI..sub.G =V.sub.RS (&gt;.PHI..sub.B), and the source potential V.sub.S is reset to GND so that V.sub.G =.PHI..sub.B.
(2) At a time t.sub.2
The voltages of the pulses .PHI..sub.G and .PHI..sub.R become equal to GND, the gate potential V.sub.G becomes a reverse-biased voltage, as given by the following equation, so as to initiate optical integration: ##EQU1## where C.sub.j =C.sub.GS +C.sub.GD
(3) a time t.sub.3
This is the time for the optical integration. At this time, a photoelectric charge Q.sub.ph generated by irradiation of light is accumulated in the gate capacity (C.sub.G +C.sub.J). This photo-electric charge Q.sub.ph is given by the equation: EQU Q.sub.ph =G.sub.L .multidot.A.multidot.P.multidot.t.sub.int =G.sub.L .multidot.A.multidot.E (2)
Where G.sub.L represents the generation rate (.mu.A/.mu.W), A represents the light receiving area (cm.sup.2), P represents the irradiance of the light (.mu.W/cm.sup.2), tint represents the integration time (S), and E represents the exposure (E=P t.sub.int)
The gate voltage V.sub.G is obtained from Equations (1) and (2) and is represented by the following equation: ##EQU2##
(4) At a time t.sub.4
If, when .PHI..sub.G =V.sub.RD, the gate potential V.sub.G is V.sub.G4 : ##EQU3## If V.sub.G4 &gt;V.sub.P, a drain current flows through the picture-element SIT, thereby charging the source line capacitance C.sub.S. In the above inequality, V.sub.P is the potential difference between the gate and the source at which a drain current of the picture-element SIT begins to flow. This is called a pinch-off voltage. The above charging lasts until the potential difference V.sub.GS between the gate and the source becomes equal to V.sub.P. Therefore, the source potential V.sub.S is given by Equation (5): ##EQU4## Since V.sub.P &lt;.PHI..sub.B, the rate of a current flowing from the p.sup.+ gate region to the n.sup.+ source region of the picture-element SIT is very small.
(5) At a time t.sub.5
The horizontal scanning pulse .PHI..sub.S reaches high level, and the source line is connected to a load resistance R.sub.L via a MOS transistor T.sub.S (on resistance: R.sub.ON). The Output V.sub.OUT thereof changes with time and is represented by Equation (6): ##EQU5##
FIG. 5 shows details of changes with time in the gate potential V.sub.G, the source potential V.sub.S and the output V.sub.OUT of the picture-element SIT observed when the horizontal scanning pulse .PHI..sub.S reaches high level. As shown in FIG. 5, when the horizontal scanning pulse .PHI..sub.S reaches high level, the p.sup.+ gate and the n.sup.+ source of the picture-element SIT are set in the forward direction, so that a pn-diode current flows therethrough and a signal charge which has been accumulated in the gate capacity flows into the source. That is, the optical signal charge is destroyed so that both the gate potential V.sub.G and the source potential V.sub.S decrease Therefore, the output V.sub.OUT given by Equation (6) is smaller than a value obtained by substituting Equation (5) for V.sub.s (t) of Equation (6). .DELTA.t represents a period of time in which the MOS transistor Ts is completely switched on after the horizontal scanning pulse .PHI..sub.S has risen, that is, a period of time in which the output V.sub.OUT reaches a peak value V.sub.OUT after the moment at which the pulse .PHI..sub.S rises.
As is clear from the above description, in the conventional solid-state image pickup apparatus using SITs as photoelectric conversion elements, optical signals are read out in the manner of so-called destructive readout in which an optical signal charge is discharged to read the signal. The output current thereof is remarkably larger than that of MOS sensors, but this method cannot answer the need for further increase in the output level.